A general system that implements a graphics pipeline system is illustrated in Prior Art FIG. 1. In this system, data source 10 generates a stream of expanded vertices defining primitives. These vertices are passed one at a time, through pipelined graphic system 12 via vertex memory 13 for storage purposes. Once the expanded vertices are received from the vertex memory 13 into the pipelined graphic system 12, the vertices are transformed and lit by a transformation module 14 and a lighting module 16, respectively, and further clipped and set-up for rendering by a rasterizer 18, thus generating rendered primitives that are displayed on display device 20.
During operation, the transform module 14 may be used to perform scaling, rotation, and projection of a set of three dimensional vertices from their local or model coordinates to the two dimensional window that will be used to display the rendered object. The lighting module 16 sets the color and appearance of a vertex based on various lighting schemes, light locations, ambient light levels, materials, and so forth. The rasterization module 18 rasterizes or renders vertices that have previously been transformed and/or lit. The rasterization module 18 renders the object to a rendering target which can be a display device or intermediate hardware or software structure that in turn moves the rendered data to a display device.
Antialiasing is a method for improving the realism of an image by removing jagged edges during rendering. Such jagged edges appear because a computer monitor has discrete pixels, that cannot adequately display image features that are finer than pixel resolution. FIGS. 1A–1 illustrates an image 10 that is subject to aliasing.
If one puts a grid over the image 10 of FIGS. 1A–1 and only colors those squares that are entirely within the circle, aliasing occurs. FIGS. 1A–2 illustrates the image 10 of FIGS. 1A–1 subject to aliasing 12. The “blockiness” that is shown is the result of aliasing, and is exactly what happens when you try to display a circle on a computer screen.
FIGS. 1A–3 illustrates the manner in which aliasing may be assuaged somewhat by using a finer grid 14. Still, the problem is not completely alleviated with the finer grid 14, and more expensive hardware is necessary to increase the resolution of the computer screen to accommodate the finer grid 14.
Because of the digital nature of computers, it is not possible to completely eliminate aliasing. However, it is possible to minimize its effects. One solution involves treating each pixel as a finite square area, rather than as a mere point on the screen. Either by computing the color at many points within a pixel, or by keeping track of multiple primitives' partial coverage overlapping a pixel, the final pixel color can be a weighted average of all relevant portions. By capturing information from many points within a pixel, details too fine to be expressed by one-per-pixel sampling make an appropriate contribution.
Continuing with the image 10 of FIGS. 1A–1 though 1A–3, the antialiased circle might then be represented with reference to FIGS. 1A–4. FIGS. 1A–4 illustrates the manner in which antialiasing 16 helps eliminate jagged edges, thus making an image seem more realistic.
FIGS. 1B–1 illustrates a non-integrated prior art graphics system implementation that does not employ any antialiasing process. As shown, an off-chip process module 20 (i.e. rasterizer) has a first dedicated memory 22. In use, the off-chip process module 20 feeds a pixel fragment processor 24, having its own second dedicated memory 26. Without any aliasing preventive measures, the off-chip process module 20 and the pixel fragment processor 24 both communicate data to and from their respective memories at a similar rate in a parallel manner.
FIGS. 1B–2 illustrates a non-integrated prior art graphics system implementation that employs an antialiasing process. In operation, the pixel fragment processor must access graphics data in the second dedicated memory 26 at an accelerated rate (i.e. ×4) to accommodate antialiasing sampling requirements. This bottleneck slows down computer graphics processing, and further leaves the first dedicated memory 22 idle three out of four clock cycles.
FIGS. 1B-3 illustrates a non-integrated prior art graphics system implementation that employs an antialiasing process. Since the implementation is not integrated, additional post-filtering logic 30 must be employed to execute any postfiltering routines after the rasterizer has rendered the image. This detrimentally affects cost since much of the logic is redundant with respect to that of the off-chip process module 20.
Thus, the incorporation of antialiasing in a non-integrated graphics system implementation suffers from a lack of efficient utilization of memory bandwidth (See FIGS. 1B–2), and further requires expensive additional logic (See FIGS. 1B–3).
Generally, integration is often limited by the cost of implementing and manufacturing multiple processing modules on a single chip. In the realm of graphics processing, attempts to integrate modules to increase speed can make costs prohibitive, since the cost of an integrated circuit increases rapidly as die size increases. High performance transform and lighting engines alone require significant area and are thus expensive to implement on-chip. Additional on-chip logic for additional functionality compounds the size and can raise the die cost to prohibitive levels.
There is therefore a need for a cost-effective computer graphics pipeline integration which overcomes the shortcomings inherent to antialiasing on a non-integrated platform.